1. Field of the Invention
The present invention relates to a polyphase clock generator that is able to generate a polyphase clock signal based on reference clock signals having different phases. In particular, the present invention relates to a polyphase clock generator for use in clock data recovery (CDR) in transmission and reception of digital signals.
The present application claims priority on Japanese Patent Application No. 2011-183290, the content of which is incorporated herein by reference.
2. Description of the Related Art
In order to transmit and receive digital signals between LSI chips, it is necessary for a receiver to determine data bits at correct timings. For this reason, it is necessary to arrange an exclusive signal line of transmitting a timing signal (or a clock signal) independently of other signal lines for transmitting data signals. Herein, a timing signal line should be wired along data signal lines, and therefore it is necessary to implement wiring occupying a relatively large area on a substrate.
Recently, a high-speed serial transmission and reception system precluding a timing signal line has been developed with a transmitter which superposes a timing signal on data signals and a receiver which detects edges of data signals and adjusts the phase of an internal reference clock so as to recover timing information. This process is generally referred to as clock data recovery (CDR). A receiver may include a CDR circuit for use in clock data recovery.
The configuration of a CDR circuit can be realized according to a phase synchronization method (e.g. a Phase-Locked Loop (PLL) method), a ring oscillator method, and a phase interpolation method. Each method has its own merits and demerits. There is a recently increasing tendency that a digital signal transmission and reception system employs a CDR circuit according to the phase interpolation method. PLT 1 discloses a polyphase clock generator that is able to generate a polyphase clock signal having an arbitrary phase by way of phase interpolation on reference clock signals having different phases.
FIG. 11 is a block diagram showing an example of a polyphase clock generator 9 installed in a CDR circuit. The polyphase clock generator 9 includes a four-to-eight (4/8) phase converter 91, a phase selector 92, and a CDR controller 93.
The 4/8 phase converter 91 receives four reference clock signals IN000, IN090, IN180, and IN270 from an external circuit (not shown). Herein, the reference clock signals IN090, IN180, IN270 have the same frequency as the reference clock signal IN000 with phase differences of 90°, 180°, 270° relative to the reference clock signal IN000. Based on the four reference clock signals IN000, IN090, IN180, and IN270, the 4/8 phase converter 91 produces eight clock signals OUT0 to OUT7 which have the same frequency as the reference clock signals IN000, IN090, IN180, IN270 but with different phases. The 4/8 phase converter 91 includes buffers 911-1 to 911-4, delay buffers 912-1 to 912-4, and phase interpolators (PI) 913-1 to 913-4.
Specifically, the reference clock signals IN000 and IN180 are supplied to the phase interpolators 913-1 and 913-4 via the buffer 911-1. Additionally, the reference clock signals IN000 and IN180 are supplied to the phase interpolators 913-1 and 913-2 via the buffer 911-2 and the delay buffers 912-1 and 912-2. A phase difference of 45° is applied between the reference clock signals IN000 and IN180 while passing through the delay buffers 912-1 and 912-2.
The reference clock signals IN090 and IN270 are supplied to the phase interpolators 913-2 and 913-3 via the buffer 911-3. Additionally, the reference clock signals IN090 and IN270 are supplied to the phase interpolators 913-3 and 913-4 via the buffer 911-4 and the delay buffers 912-3 and 912-4. A phase difference of 45° is applied between the reference clock signals IN090 and IN270 while passing through the delay buffers 912-3 and 912-4.
The phase interpolators 913-1 to 913-4 multiplex four reference clock signals IN000 to IN270, which are supplied thereto via the buffers 911-1 to 911-4 and the delay buffers 912-1 to 912-4, so as to produce eight clock signals OUT1 to OUT7 with different phases.
The phase selector 92 includes a selector 921 and phase interpolators 922-1 to 922-4. Under control of the CDR controller 93, the selector 921 selectively combines eight clock signals OUT0 to OUT7, which are received from the 4/8 phase converter 91, so as to produce combined clock signals subsequently supplied to the phase interpolators 922-1 to 922-4. The phase interpolators 922-1 to 922-4 further combine the combined clock signals, which are received from the selector 921, so as to produce eight clock signals CLK000, CLK045, CLK090, CLK135, CLK 180, CLK225, CLK270, and CLK315 with difference phases.
Based on edge samples and data samples which are sampled with a CDR circuit (not shown), the CDR controller 93 generates control signals SELC and SELP to the phase selector 92, thus controlling the phases of the clock signals CLK00 to CLK315.
The polyphase clock generator 9 utilizes the functions of the phase interpolators 913-1 to 913-4 and the interpolators 922-1 to 922-4, each of which is able to generate an intermediate phase signal having an intermediate phase between the phases of two signals. In the output stage of circuitry, the phase interpolators 922-1 to 922-4 generate the consecutive phases of clock signals by way of combinations of combined clock signals output from the selector 921.
Each of the phase interpolators 913-1 to 913-4 and 922-1 to 922-4 has a function of generating a clock signal with an intermediate phase combining two clock signals, wherein each phase interpolator should be optimized in terms of the size of transistors (e.g. a ratio of width (W)/length (L)) fabricated therein as well as a leading time and a trailing time of a clock signal supplied thereto in conformity with a clock frequency which is determined in the design stage.
When the polyphase clock generator 9 designed based on a high clock frequency is utilized in a low clock frequency range, it is necessary to arrange a frequency divider following the polyphase clock generator 9. FIG. 12 is a block diagram showing an example of a polyphase clock generator 9A adapted to a plurality of clock frequencies, wherein parts identical to those shown in FIG. 11 are denoted using the same reference signs. The polyphase clock generator 9A includes a 1/2 frequency divider 94 following the same configuration as the polyphase clock generator 9.
The polyphase clock generator 9A produces eight clock signals CLK000, CLK045, CLK090, CLK135, CLK180, CLK225, CLK270, and CLK315, wherein the frequency divider 94 should implement a frequency dividing function adapted to eight clock signals, which in turn increases power consumption and a circuit mounting area on a chip. Generally speaking, when a phase interpolator receives two clock signals with phases which are lower than the clock frequency (which is determined in the design stage), it may undergo an increasing phase difference between two clock signals so that the output waveform thereof may be increasingly distorted. In the worst scenario, a phase interpolator may produce an output waveform including stepwise differences, thus degrading jitter characteristics.
FIGS. 13A and 13B show examples of output waveforms of phase interpolators involving distortions. These waveforms are measured using a phase interpolator with a clock frequency of 2.5 GHz, which is adjusted in the frequency to produce output signals (fout) at 2.5 GHz and 1.25 GHz. The output waveforms of FIG. 13B are softened or dulled compared to the output waveforms of FIG. 13A. FIG. 13A shows stepwise differences occurring during variations of output signals at fout=1.25 GHz. FIG. 13B shows output waveforms which are dulled in order to reduce stepwise differences occurring during variations of output signals, thus significantly degrading jitter characteristics.